A. Field of the Invention
This application relates to control storage devices, in general, and to programmable logic arrays in particular.
B. Description of the Prior Art
In the microprocessor art, control stores have been implemented in the past with read-only memories (ROM). A read-only memory as a control store requires exhaustive coding of all of its address input lines. This requirement produces a large read-only memory array which takes up very valuable space on a microprocessor chip.
Recently, programmable logic arrays have been used as control stores. A programmable logic array is basically an array of logic gates all formed on a single semiconductor chip. The gates can be joined together to form any combinatorial logic function desired. That is, given a certain digital input, the collection of gates will deliver a particular digital output. In operation, input signals first pass through a series of AND gates, resulting in a predetermined number of product terms being formed. In prior art programmable logic arrays and field programmable logic arrays, the number of input gates runs anywhere from about 40 to 150. The product signals then pass to a set of OR gates to become the final output signals.
In all the prior art programmable logic arrays, the AND gates are implemented in one array and the OR gates are implemented in another array. Thus, when a programmable logic array is located on a semiconductor chip, it is necessary to have all of the control lines for receiving the final output signals connected to the single OR array outputs. This produces a definite disadvantage in that the control lines must take up valuable silicon real estate on the chip in order to be successfully routed from the OR section to the devices receiving any of the control signals. In other words, it may be necessary to make the control lines longer than is desirable for efficient use of space on the chip.